Recently, since the requirement of transceiver of low power and low cost is steadily on the increase, so the technology of mainstream IC competitively concentrates on how to realize further more functions of radio frequency on one single chip. Except making integrated circuit be able to arrange on the package substrate, the external circuit connected by the external legs of package substrate must be electrically connected to the integrated circuit. So, when packaging the integrated circuit, the technology of pad has become an important factor that influences the yield and quality of a product. This pad adapted for providing electric connection between the integrated circuit and the external circuit is usually arranged in the metal zone around the IC die. When the pad is formed, the metal connecting wire must contact with the pad accurately and connect to the external legs of the IC packaging substrate. Because of the limitation of the prior arts and the characteristics of metal connecting wire and pad, the area of pad is sometimes too large to occupy too much area of chip. Furthermore, during high frequency, the performance of the integrated circuit is influenced because the equivalent electric capacitance is too large.
Additionally, because of the market growth of communication IC recently, the operational frequency of integrated circuit is also growing in indexing type. The low noise and low loss of high frequency signal are always the pursuing goals for communication IC.
In 1987, the U.S. Pat. No. 4,636,832 “Semiconductor device with an improved bonding section” proposed a design method of the pad of integrated circuit. Please refer to FIG. 1, which is a cross-sectional diagram of the IC device disclosed in the U.S. Pat. No. 4,636,832. The characteristic of this prior art is that the semiconductor element 10 is arranged below the pad 15. Although it may reduce the area of layout, this kind of pad can not be adapted to high frequency circuit with low noise because the noise coming from the semiconductor substrate 20 will directly influence the signal of high frequency when it passes through the pad.
To overcome the tensile and tension of bonding, the U.S. Pat. No. 5,248,903 “Composite pads for semiconductor devices” proposed a kind of pad. Please refer to FIG. 2, which is the cross-sectional diagram of the IC device disclosed in the U.S. Pat. No. 5,248,903. Wherein, the pad 30 has at least two layers of electric-conduction layer 30a and 30c and a connection layer 30b. But, this kind of pad is not adapted for the signals of high frequency and low noise because the noise of semiconductor substrate 35 will directly influence the quality of signal.
The U.S. Pat. No. 5,502,337 “Semiconductor device structure including multiple interconnection layers with interlayer insulating films” proposed a different designing method for pad. Please refer to FIG. 3, which is a cross-sectional diagram for the IC device disclosed in the U.S. Pat. No. 5,502,337, which arranges the connection layer 40a in the pad 40 around the bonding zone 45. When the integrated circuit is manufactured, a bonding zone of arc shape will be formed on the pad 40 to thereby enhance the bonding adherence. However, the technology of current integrated circuit has stepped into the levels of sub micrometer or deep sub micrometer, and CMP (Chemical-Mechanical Polish) is already a standard procedure for current semiconductor process. So, this kind of prior art no longer generates original effectiveness in current semiconductor process, besides this technique has the same drawback as that of previous techniques; i.e., it can not separate the noise coming from the semiconductor substrate 50.
From above discussion, we know that the prior arts described there are unable to propose an effective solution that aims for the high frequency, low noise and bonding adherence. Therefore, the emphasis of the invention is to provide a pad structure adapted for a integrated circuit of high frequency and low noise to lower down the equivalent electric capacitance and enhance the bonding adherence, such that it can prevent the entire pad from being drawn out of the semiconductor chip by the tension generated in the bonding procedure.